Guideline for evaluating bias temperature instability of silicon carbide metal-oxide-semiconductor devices for power electronic conversion
1Key Takeaways
This Final Draft International Standard is an up to 6 weeks' pre-release of the official publication. It is available for sale during its voting period: 2025-11-28 to 2026-01-09. By purchasing this FDIS now, you will automatically receive, in addition, the final publication. IEC 63601:2026 covers SiC-based PECS devi…
2Expert Interpretation
This article provides an in-depth interpretation of the IEC 63601:2025 international standard, offering a comprehensive analysis of bias temperature instability (BTI) assessment methods for silicon carbide MOS devices. It covers threshold voltage measurement specifications, a comparison of five BTI testing methods, lifetime prediction models, and implementation recommendations, providing standardized guidance for the reliability assessment of power electronic conversion devices.
Background and Technological Evolution of Standard Development
With the widespread application of third-generation semiconductor silicon carbide (SiC) in high-voltage and high-power fields such as new energy vehicles, rail transit, and smart grids, the long-term reliability of its metal-oxide-semiconductor (MOS) devices has become a focus of industry attention. The IEC 63601:2025 standard, "Guideline for the Evaluation of Bias Temperature Instability of Silicon Carbide Metal-Oxide-Semiconductor Devices," released by the International Electrotechnical Commission (IEC) in 2025, fills the international standardization gap in this field. This standard is based on the JEDEC JEP184 standard and adopts a fast-track procedure, reflecting the urgency of technological development.
Compared with traditional silicon-based devices, SiC MOSFETs and IGBTs exhibit more complex threshold voltage instability phenomena under high temperature and high field strength.
The standards-setting committee IEC/TC47 (Semiconductor Devices) brought together experts from major semiconductor research and development institutions in South Korea, the United States, and Europe, and completed technical coordination over three years. The technical evolution of this standard is mainly reflected in three aspects: **refinement of measurement methods**, **standardization of test conditions**, and **scientific interpretation of data**.
Core Concepts and Terminology
This standard establishes a complete terminology system for bias temperature instability (BTI) assessment. Key concepts include:
| Terminology | Definition | Measuring Significance | Typical Impact | ||
|---|---|---|---|---|---|
| Threshold Voltage (VT) | Minimum Gate Voltage Required for Device Turn-On | Core Parameter of Device Switching Characteristics | Drift-Induced Changes in Switching Losses | ||
| Positive Bias Temperature Instability (PBTI) | VT Drift Over Time at Positive Gate Voltage | Assessing Positive Bias Operating Reliability | Increased On-Resistance|||
| Negative Bias Temperature Instability (NBTI) | VTDrift Over Time under Negative Gate Voltage | Evaluating Reliability of Negative Bias Operation | Deterioration of Turn-Off Characteristics | ||
| Threshold Hysteresis (VTHYST) | VTDifference in Bidirectional Scan | Characterizing Interface Trap Density | Reduced Dynamic Response Speed | ||
| Fast Transient Effects | Fast Recovery of VT after Gate Voltage Switching | Distinguishing Between Recoverable and Permanent Damage | Affecting Switching Transient Accuracy |
| Method Name | Core Principle | Applicable Scenarios | Test Time | Accuracy Level | Standard Illustration |
|---|---|---|---|---|---|
| General MSM Method | Measurement-Stress-Measurement Cycle | Basic Screening Test | Medium | Basic Level | Figure 9-10 |
| Fast Leakage Current Method | Rapid ID Sampling | Online Monitoring | Short | Engineering Level | Figure 11-12 |
| Grid Scan MSM Method | Full Transfer Characteristic Scan | Mechanism Study | Long | Research Level | Figure 13-14 |
| Pre-conditioning Method | Standardized Pre-processing | Mass Production Testing | Medium Level | Production Line Level | Figure 15-17 |
| Triple Detection Method | Three VT Measurements | High-Precision Evaluation | Very Long | Certification Level | Figure 19 |
From a technological evolution perspective, these methods embody a gradient design from **simple pass/fail testing** to **full-parameter characterization**. For example, the triple detection method (Chapter 10) can distinguish between: 1) permanent drift (interface state generation); 2) recoverable drift (charge trapping); and 3) hysteresis effects (slow-state response) through a sequence of first VT detection → hysteresis measurement → second VT detection. This refinement provides multidimensional data for device failure analysis.
Industrial Application Comparison: Method Selection in Photovoltaic Inverters
For photovoltaic inverters with a service life requirement of 25 years or more, manufacturers need to evaluate the long-term reliability of SiC MOSFETs under day-night temperature cycling.
Practice shows that: General MSM method: Suitable for rapid screening on production lines; 1000 hours of testing can cover 90% of early failures. Gate scan MSM method: Used for design verification; a VT-temperature model is established through scanning the entire temperature range (-40°C to 150°C). Triple detection method: Used for certification testing, especially to meet the reliability testing requirements of IEC 63275-1. Appendix B of the standard provides detailed measurement examples. Figures B.6-B.7 show typical response curves of the triple detection method under PBTI/NBTI stress, providing a benchmark for data interpretation. Life Prediction Model and Failure Determination Section 4.5 and Appendix D of the standard systematically explain the BTI life prediction model, which is the core of reliability assessment. Based on the power-law model: ΔVT = A·tn·exp(-Ea/kT)·exp(γVG) Key parameters include: Time exponent n: Typical value for SiC devices is 0.1-0.3, lower than 0.25-0.5 for silicon-based devices. Activation energy Ea: Approximately 0.8-1.2 eV for PBTI and approximately 0.6-1.0 eV for NBTI. Electric field acceleration factor γ: Typical value is 2-4 decade/V. Standard Figures 7-8 show typical NBTI and PBTI drift curves and their power-law fit. It is particularly important to note that the BTI drift of SiC devices often exhibits a **two-stage characteristic**: rapid initial drift (t < 1s) and slow long-term drift (t > 1000s). Standards recommend using long-term drift data for lifetime extrapolation to avoid premature failure determination.
| Failure Modes | Physical Mechanisms | Detection Methods | Recovery Characteristics | Preventive Measures |
|---|---|---|---|---|
| Permanent VTDrift | Interface State Generation | Triple Detection Method | Irreversible | Optimized Oxidation Process |
| Recoverable VTDrift | Charge Trapping | Hysteresis Method | Partial Recovery | Interface Passivation |
| Hysteresis Window Enlargement | Slow-State Response | Gate Scan Method | Temperature Dependence | Reduced Interface Density |
| Fast Transient Effects | Near-Interface Trap | Fast Leakage Current Method | Fast Recovery | Optimized Gate Oxide Quality |
The standard explicitly does not define specific failure criteria, leaving this to negotiation between device manufacturers and users. However, it provides standardized data acquisition methods to ensure the comparability of data from different sources. Typical industrial practice is: a VT drift exceeding the initial value ±20% or a hysteresis window exceeding 1V is used as a warning threshold.
Standard Implementation Recommendations and Best Practices
Based on the content of this standard, the following implementation recommendations are provided for different stakeholders:
For Device Manufacturers
- Standardization of Test Conditions: Establish internal test specifications based on Chapter 4 of this standard to ensure consistency of data across different batches.
- Method Selection Matrix: Select appropriate BTI evaluation methods according to product grade (consumer, industrial, automotive).
- Completeness of Data Recording: Record complete temperature, voltage, and time series data according to the sampling guidelines in Appendix A.
- Accelerated Test Design: Design reasonable acceleration factors based on the model in Appendix D to avoid overtesting or undertesting.
For System Integrators
- Supplier Evaluation Standards: Require suppliers to provide BTI test reports based on IEC 63601, focusing on test method details.
- Application Condition Mapping: Map actual application conditions (temperature profile, voltage stress) to standard test conditions
- Derating Design Basis: Develop reasonable voltage and temperature derating specifications based on BTI drift data
- Lifetime Prediction Verification: Set up monitoring points in the actual system to verify the accuracy of accelerated test lifetime prediction
For Test Laboratories
- Equipment Calibration Requirements: Ensure voltage measurement accuracy ≤1mV and temperature control accuracy ≤±0.5°C
- Test Sequence Programming: Strictly program test sequences according to the standard diagram (Figure 9-19), especially timing control
- Data Report Template: Develop standardized test report templates containing all necessary parameters and raw data
- Uncertainty Analysis: Perform uncertainty analysis on measurement results, especially long-term drift measurements
- Test Standards: Fully compliant with IEC 63601, while also referencing IEC 63275-1
- Test Methods: Triple testing method (Chapter 10), testing 3 samples at each stress point
- Stress Conditions: Temperatures 125°C, 150°C, 175°C; Gate voltages +25V, -10V (corresponding to the maximum value in actual applications)
- Test Duration: 1000 hours for each condition, extrapolated to a 30-year service life
- Acceptance Standards: VT drift <±15%, hysteresis window <0.8V
- Evaluation of Ultra-High Voltage Devices: 6.5kV devices require higher gate stress, and existing test equipment may need to be upgraded
- Evaluation of Dual-Gate Structures: New SiC devices adopt a dual-gate structure, requiring expanded test methods
- Dynamic BTI Evaluation: In practical applications, gate voltage switches rapidly, requiring the development of dynamic BTI test methods
- Coupling with Other Failure Mechanisms: The coupling effect of BTI with gate oxide breakdown and hot carrier injection needs to be studied
Implementation Case: Compliance Testing of Rail Transit Traction Systems
A rail transit vehicle manufacturer developed a BTI test plan for its 3.3kV SiC MOSFET traction converter:
Through standardized testing, the manufacturer successfully obtained EN 50155 railway application certification. The test data was accepted by multiple customers, reducing the cost of repeated testing.
Technology Development Trends and Standard Outlook
As SiC devices develop towards higher voltages (3.3kV, 6.5kV) and lower specific on-resistance, BTI evaluation faces new challenges:
The stability date specified in this standard is 2028, at which time it will be revised according to technological developments.
Possible revision directions include: Adding dynamic BTI testing methods; Extending to wide bandgap devices (GaN, Ga2O3); Incorporating in-situ monitoring technology; Combining with artificial intelligence data analysis. As the first international standard for BTI evaluation of silicon carbide MOS devices, the release of IEC 63601:2025 marks a new stage of standardization in the reliability evaluation of third-generation semiconductors. By standardizing testing methods, regulating data reporting, and establishing comparable benchmarks, this standard will strongly promote the reliable application of silicon carbide power devices in key areas such as new energy, electric vehicles, and industrial control, providing technical support for the global carbon neutrality goal.